Compiler Technical Director/Lead

Santa Clara, California
Work Type: Full Time



About us 

If you are following the evolution of the leading approach in deep learning powered AI, the renaissance in NLP as well as the next disruption in computer vision, you likely know it’s all about Transformer based models..  They are powering neural nets with billions to trillions of parameters and existing silicon architectures (including the plethora of AI accelerators) are struggling to varying degrees to keep up with exploding model sizes and their performance requirements.   More importantly, TCO considerations for running these models at scale are becoming a bottleneck to meet exploding demand.  Hyperscalers are keen on how to gain COGS efficiencies with the trillions of AI inferences/day they are already serving, but certainly for addressing the steep demand ramp they are anticipating in the next couple of years. d-Matrix is addressing this problem head on by developing a fully digital in memory computing accelerator for AI inference that is highly optimized for the computational patterns in Transformers.  The fully digital approach removes some of the difficulties of analog techniques that are most often touted in pretty much all other in-memory computing AI inference products.  d-Matrix’s AI inference accelerator has also been architected as a chiplet, thereby enabling both a scale-up and scale-out solution with flexible packaging options. The d-Matrix team has a stellar track record in developing and commercializing silicon at scale as senior execs at the likes of Inphi, Broadcom, and Intel.   Notably, they recognized early the extremely important role of programmability and the software stack and are thoughtfully building up the team in this area even since before their Series A. The company has raised $44m in funding so far and has 70+ employees across Silicon Valley, Sydney and Bengaluru.

Why d-Matrix 

We want to build a company and a culture that sustains the tests of time. We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally. We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey. We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge. The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business.

The role: Compiler Technical Director/Lead 

The Compiler Technical Director/Lead role is driving the design and implementation of the MLIR-based compiler framework. In this role, you will be overseeing the development of the compiler that partitions and maps large-scale NLP models to our scalable, multi-chiplet, parallel processing architecture with hundreds of digital in-memory tensor processors, vector processors, data shaping processors and both on-chip and off-chip memory. The compiler will also coordinate the scheduling of parallel tasks onto the processors, data movements and inter processor synchronization. The many-pass compiler architecture requires graph optimization passes, constant folding, data reshaping, padding, tiling and various other backend-specific operations. The software will support a split offline/online mapping process with just-in-time mapping to chiplets, processors and DDR memory channels. 

This role requires collaborating with the HW and SW architecture team, the Pytorch front-end pre-processing team, the data science numerics team, AI kernel team, SW test group, the benchmark group and the teams developing the various simulator and emulation platforms. It is central to the overall efficiency of the solution. As such, we are seeking an AI compiler expert with experience in the TVM, Glow or preferably, the MLIR project. Also important is familiarity with the LLVM project. Experience mapping graph operations to many-core processors (or spatial fabrics) would be desirable.

This role does NOT require hardware design or verification experience. That said, an understanding of the trade-offs made by processor architects when implementing accelerators for DNNs, DCNNs, transformer models and attention mechanisms is useful - especially when it comes to mapping very large NLP models to such architectures.

Experience establishing, growing and/or developing engineering teams (and software teams in particular) is a requirement to be considered for the Compiler Lead role. Experience with leading agile development methods is preferable including coordinating scrums, managing sprints and project task tracking with Kanban boards or similar. Experience running code reviews, bug tracking meetings, familiarity and experience with CI/CD flows is also a requirement. Managing interdependencies with other teams in order to meet milestones and target levels of performance. The candidate should have excellent documentation and presentation skills.

This role includes technical leadership aspects: specifically the motivation, engagement, goal setting, performance tracking, objective setting and performance management.

The role requires a graduate degree in Computer Science or equivalent.


Bay Area (preferred), Toronto, or Seattle

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