THE ROLE: SR PRINCIPAL/PRINCIPAL PACKAGING ENGINEER – India or Bay Area
If you are following the evolution of the leading approach in deep learning powered AI, the renaissance in NLP as well as the next disruption in computer vision, you likely know it’s all about Transformer based models.. They are powering neural nets with billions to trillions of parameters and existing silicon architectures (including the plethora of AI accelerators) are struggling to varying degrees to keep up with exploding model sizes and their performance requirements. More importantly, TCO considerations for running these models at scale are becoming a bottleneck to meet exploding demand. Hyperscalers are keen on how to gain COGS efficiencies with the trillions of AI inferences/day they are already serving, but certainly for addressing the steep demand ramp they are anticipating in the next couple of years. d-Matrix is addressing this problem head on by developing a fully digital in memory computing accelerator for AI inference that is highly optimized for the computational patterns in Transformers. The fully digital approach removes some of the difficulties of analog techniques that are most often touted in pretty much all other in-memory computing AI inference products. d-Matrix’s AI inference accelerator has also been architected as a chiplet, thereby enabling both a scale-up and scale-out solution with flexible packaging options. The d-Matrix team has a stellar track record in developing and commercializing silicon at scale as senior execs at the likes of Inphi, Broadcom, and Intel. Notably, they recognized early the extremely important role of programmability and the software stack and are thoughtfully building up the team in this area even since before their Series A. The company has raised $44m in funding so far and has 70+ employees across Silicon Valley, Sydney and Bengaluru.
We want to build a company and a culture that sustains the tests of time. We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally. We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey. We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge. The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business.
• Responsible for the thermal/mechanical/electrical design, analysis, and development of Single-Chiplet and MultiChiplet Packaging.
• Responsible for package design and design flow development for advanced packaging technologies in a cross-functional team.
• Work with 3rd Party Design Services team to ensure all packaging design requirements are verified.
• Work with the Si and Board design teams to define and implement a co-design strategy which would optimize product performance and cost at the package and system level.
• Design and develop package and interconnect methods in the areas of wafer level, flip-chip, multi-chip module.
• Participate in packaging roadmap development and focus on execution.
• Establish and maintain package design rules.
• Master’s degree and/or PhD in Electrical Engineering, or related fields with at least 10 years of related professional experience preferred.
• Has strong technical background in design and electrical analysis.
• Understand packaging technology development FMEAs and product packaging requirements - both physical and electrical.
• Understand the interaction of Si +Package and Board. Exposure to high-speed board design is preferred.
• Experience with design and electromagnetic simulation tools: Mentor, Cadence tools, SPICE, Ansys tools etc.
• Experience and knowledge with assembly process, test and characterization techniques would be an added advantage.
India (preferably Bengaluru) or Bay Area